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DATA SHEET
MOS INTEGRATED CIRCUIT
PD178004A, 178006A, 178016A, 178018A
8-BIT SINGLE-CHIP MICROCONTROLLERS
The PD178004A, 178006A, 178016A and 178018A are 8-bit single-chip CMOS microcontrollers that incorporate hardware for digital tuning systems. The CPU uses the 78K/0 architecture, which makes it easy to implement high-speed access to internal memory and control of peripheral hardware. Also, the instructions used are the high-speed 78K/0 instructions, suitable for system control. The rich assortment of peripheral hardware includes an input/output port, 8-bit timer, A/D converter, serial interface, power-ON clear circuits, as well as a pre-scaler for digital tuning, a PLL frequency synthesizer and a frequency counter. The PD178P018A, one-time PROM or EPROM versions which can be operated in the same supply voltage range as for the mask ROM versions, and various development tools, are also available. For more information on functions, refer to the following User's Manuals. Be sure to read them when designing. PD178018A Subseries User's Manual: to be prepared 78K/0 Series User's Manual Instruction: U12326E
FEATURES
* Internal high-capacity ROM and RAM
Items Product Name Program Memory ROM 32 Kbytes 48 Kbytes 2 048 bytes 60 Kbytes Internal High-Speed RAM 1 024 bytes Data Memory Buffer RAM 32 bytes Internal Expanded RAM Not provided
PD178004A PD178006A PD178016A PD178018A
* Instruction Cycle: 0.44 s (4.5-MHz crystal oscillator used) * Large array of on-chip peripheral hardware General-purpose input/output port, A/D converter, serial interface, timer, frequency counter, power-ON clear circuits. * On-chip hardware for a PLL frequency synthesizer. Dual modulus pre-scaler, programmable divider, phase comparator, charge pump. * Vector interrupt sources: 17 * Supply Voltage: VDD = 4.5 to 5.5 V (during PLL operation) VDD = 3.5 to 5.5 V (during CPU operation, when the system clock is fX/2 or lower) VDD = 4.5 to 5.5 V (during CPU operation, when the system clock is fX)
The information in this document is subject to change without notice. Document No. U12641EJ1V0DS00 (1st Edition) Date Published July 1997 N Printed in Japan
(c)
1997
PD178004A, 178006A, 178016A, 178018A
APPLICATIONS Car stereo, home stereo systems. ORDERING INFORMATION Part Number Package 80-pin plastic QFP 80-pin plastic QFP 80-pin plastic QFP 80-pin plastic QFP (14 (14 (14 (14 x 14 mm, 0.65-mm pitch) x 14 mm, 0.65-mm pitch) x 14 mm, 0.65-mm pitch) x 14 mm, 0.65-mm pitch)
PD178004AGC-xxx-3B9 PD178006AGC-xxx-3B9 PD178016AGC-xxx-3B9 PD178018AGC-xxx-3B9
Remark
xxx denotes the ROM code number. Also, the ROM code number becomes Exx when the I2C bus is used.
PD178018A SUBSERIES AND PD178003 SUBSERIES EXPANSION
80 pins
PD178P018A Note
PROM : 60 KB
RAM : 3 KB
80 pins
PD178018A
ROM : 60 KB
RAM : 3 KB
PD178018A Subseries
80 pins
PD178016A
ROM : 48 KB
RAM : 3 KB
80 pins
PD178006A
ROM : 48 KB
RAM : 1 KB
80 pins
PD178004A
ROM : 32 KB
RAM : 1 KB
80 pins
PD178003 Note
ROM : 24 KB
RAM : 0.5 KB
PD178003 Subseries
80 pins
PD178002 Note
ROM : 16 KB
RAM : 0.5 KB
Note
Under development
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PD178004A, 178006A, 178016A, 178018A
OUTLINE OF FUNCTION
(1/2) Product name Item Internal memory ROM (ROM configuration) High-speed RAM Buffer RAM Expansion RAM General-purpose register Instruction cycle Instruction set 32 Kbytes (mask ROM) 1 024 bytes 32 bytes Not provided 2 048 bytes 48 Kbytes (mask ROM) 60 Kbytes (mask ROM)
PD178004A
PD178006A
PD178016A
PD178018A
8 bits x 32 registers (8 bits x 8 registers x 4 banks) With variable instruction execution time function 0.44 s/0.88 s/1.78 s/3.56 s/7.11 s/14.22 s (with 4.5-MHz crystal resonator) * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. : 62 pins : 1 pin : 54 pins : 4 pins : 3 pins
I/O port
Total CMOS input CMOS I/O N-ch open-drain I/O N-ch open-drain output
A/D converter Serial interface
8-bit resolution x 6 channels * 3-wire/SBI/2-wire/I2 C bus Note mode selectable : 1 channel * 3-wire serial I/O mode (with automatic transfer/receive function of up to 32 byte) : 1 channel * * * * Basic timer (timer carry FF (10 Hz)) : 8-bit timer/event counter : 8-bit timer (D/A converter: PWM output) : Watchdog timer : 1 2 1 1 channel channels channel channel
Timer
Buzzer (BEEP) output Vectored interrupt Source Test input Maskable Non-maskable Software
1.5 kHz, 3 kHz, 6 kHz Internal: 8, external: 7 Internal: 1 Internal: 1 Internal: 1
Note
When using the I2 C bus mode (including when this mode is implemented by program without using the peripheral hardware), consult your local NEC sales representative when you place an order for mask.
3
PD178004A, 178006A, 178016A, 178018A
(2/2) Product name Item PLL frequency synthesizer Division mode Two types * Direct division mode (VCOL pin) * Pulse swallow mode (VCOH and VCOL pins) 7 types selectable by program (1, 3, 5, 9, 10, 25, 50 kHz) Error out output: 2 (EO0 and EO1 pins Note 1) Unlock detectable by program * Frequency measurement * AMIFC pin: for 450-kHz count * FMIFC pin: for 450-kHz/10.7-MHz count 8-/9-bit resolution x 3 channels (shared by 8-bit timer) * HALT mode * STOP mode * Reset by RESET pin * Internal reset by watchdog timer * Reset by power-ON clear circuit (3-value detection) * Detection of less than 4.5 V Note 2 (CPU clock: fX) * Detection of less than 3.5 V Note 2 (CPU clock: fX/2 or less and on power application) * Detection of less than 2.5 V Note 2 (in STOP mode) * VDD = 4.5 to 5.5 V (with PLL operating) * VDD = 3.5 to 5.5 V (with CPU operating, CPU clock: fX/2 or less) * VDD = 4.5 to 5.5 V (with CPU operating, CPU clock: fX) * 80-pin plastic QFP (14 x 14 mm, 0.65-mm pitch)
PD178004A
PD178006A
PD178016A
PD178018A
Reference frequency Charge pump Phase comparator Frequency counter
D/A converter (PWM output) Standby function Reset
Power supply voltage
Package
Notes 1. The EO1 pin can be set to high impedance for the PD178016A and 178018A. The following shows an application example.
PD178016A PD178018A
EO0 EO1 VCOH VCOL
LPF
VCO
To Mixer
LPF : Low path filter VCO : Voltage controlled oscillator * To lock to a target frequency at high speed Setting the EO0 and EO1 pins to error out output improves the output current potential and LPF voltage control potential. * Normal state Setting only the EO0 pin to error out output maintains the LPF stable. 2. These voltage values are maximum values. Reset is actually executed at a voltage lower than these values.
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PD178004A, 178006A, 178016A, 178018A
TABLE OF CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ................................................................................................ 6 2. BLOCK DIAGRAM ........................................................................................................................... 8 3. PIN FUNCTION LIST ........................................................................................................................ 9 3.1 PORT PINS ................................................................................................................................ 9 3.2 PINS OTHER THAN PORT PINS ............................................................................................ 10 3.3 INPUT/OUTPUT CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS ..... 11 4. MEMORY SPACE .......................................................................................................................... 14 5. PERIPHERAL HARDWARE FUNCTION FEATURES .................................................................. 15 5.1 PORTS ..................................................................................................................................... 15 5.2 CLOCK GENERATOR ............................................................................................................ 16 5.3 TIMER ...................................................................................................................................... 16 5.4 BUZZER OUTPUT CONTROL CIRCUIT ................................................................................ 18 5.5 A/D CONVERTER ................................................................................................................... 19 5.6 SERIAL INTERFACES ............................................................................................................ 19 5.7 PLL FREQUENCY SYNTHESIZER ........................................................................................ 21 5.8 FREQUENCY COUNTER ........................................................................................................ 22 6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS .................................................................... 23 6.1 INTERRUPT FUNCTIONS ...................................................................................................... 23 6.2 TEST FUNCTION .................................................................................................................... 26 7. STANDBY FUNCTION ................................................................................................................... 27 8. RESET FUNCTION ........................................................................................................................ 27 9. INSTRUCTION SET ....................................................................................................................... 28 10. ELECTRICAL SPECIFICATIONS .................................................................................................. 30 11. PACKAGE DRAWINGS ................................................................................................................. 46 12. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 47 APPENDIX A. DIFFERENCES BETWEEN PD178018A AND PD178018 SUBSERIES ............... 48 APPENDIX B. DEVELOPMENT TOOLS ............................................................................................ 49 APPENDIX C. RELATED DOCUMENTS ........................................................................................... 51
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PD178004A, 178006A, 178016A, 178018A
1. PIN CONFIGURATION (TOP VIEW)
* 80-PIN PLASTIC QFP (14 x 14 mm, 0.65 mm pitch) PD178004AGC-xxx-3B9, 178006AGC-xxx-3B9 PD178016AGC-xxx-3B9, 178018AGC-xxx-3B9
P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P132/PWM0 P133/PWM1 P134/PWM2 P40 P41 P42
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
RESET VDD REGOSC X1 X2 GND REGCPU P06/INTP6 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0 P125 P124 P123 P122 P121 P120
P37 P36/BEEP P35 P34/TI2 P33/TI1 P32 P31 P30 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55 P54
Cautions 1. 2. 3. 4.
Connect Connect Connect Connect
the Internally Connected (IC) pin to GND directly. VDDPORT and VDDPLL pins to VDD. the GNDPORT and GNDPLL pins to GND. each of the REGOSC and REGCPU pins to GND via a 0.1-F capacitor.
6
GNDPORT VDDPORT P43 P44 P45 P46 P47 AMIFC FMIFC VDDPLL VCOH VCOL GNDPLL EO0 EO1 IC P50 P51 P52 P53
PD178004A, 178006A, 178016A, 178018A
AMIFC : AN10 to AN15 : BEEP : BUSY : EO0, EO1 : FMIFC : GND : GNDPLL : GNDPORT : IC : INTP0 to INTP6 : P00 to P06 : P10 to P15 : P20 to P27 : P30 to P37 : P40 to P47 : P50 to P57 : P60 to P67 : P120 to P125 : AM Intermediate Frequency Counter Input A/D Converter Input Buzzer Output Busy Output Error Out Output FM Intermediate Frequency Counter Input Ground PLL Ground Port Ground Internally Connected Interrupt Inputs Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 12 P132 to P134 : PWM0 to PWM2 : REGCPU : REGOSC : RESET : SB0, SB1 : SCK0, SCK1 : SCL : SDA0, SDA1 : SI0, SI1 : SO0, SO1 : STB : TI1, TI2 : VCOL, VCOH : VDD : VDDPLL : VDDPORT : X1, X2 : Port 13 PWM Output Regulator for CPU Power Supply Regulator for Oscillator Circuit Reset Input Serial Data Bus Input/Output Serial Clock Input/Output Serial Clock Input/Output Serial Data Input/Output Serial Data Input Serial Data Output Strobe Output Timer Clock Input Local Oscillator Input Power Supply PLL Power Supply Port Power Supply Crystal Oscillator Connection
7
PD178004A, 178006A, 178016A, 178018A
2. BLOCK DIAGRAM
TI1/P33
8-bit TIMER/ EVENT COUNTER 1 8-bit TIMER/ EVENT COUNTER 2
PORT 0
P00 6 6 P01 to P06 P10 to P15
TI2/P34
PORT 1
8-bit TIMER 3
PORT 2
8
P20 to P27
WATCHDOG TIMER
PORT 3
8
P30 to P37
BASIC TIMER SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SCK0/SCL/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 ANI0/P10 to ANI5/P15 INTP0/P00 to INTP6/P06 78K/0 CPU CORE ROM
PORT 4
8
P40 to P47
SERIAL INTERFACE 0
PORT 5
8
P50 to P57
PORT 6 SERIAL INTERFACE 1
8
P60 to P67
PORT 12
6
P120 to P125
RAM 6 A/D CONVERTER
PORT 13 D/A CONVERTER (PWM)
3
P132 to P134
3
PWM0/P132 to PWM2/P134
7
INTERRUPT CONTROL FREQUENCY COUNTER AMIFC FMIFC
BEEP/P36 RESET X1 X2 VDDPORT GNDPORT VDD
BUZZER OUTPUT RESET SYSTEM CONTROL CPU PERIPHERAL
PLL
EO0 EO1 VCOL VCOH
PLL VOLTAGE REGULATOR VOLTAGE REGULATOR VOSC VCPU
VDDPLL GNDPLL
REGOSC REGCPU GND
IC
Remark The internal ROM and RAM capacities depend on the version.
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PD178004A, 178006A, 178016A, 178018A
3. PIN FUNCTION LIST 3.1 PORT PINS
Pin Name P00 I/O Input Port 0. 7-bit input/output port. Function Input only After Reset Alternate Function Input INTP0 INTP1 to INTP6 ANI0 to ANI5
P01 to P06 I/O P10 to P15 I/O
Input/output mode can be specified bit-wise. Input Input
Port 1. 6-bit input/output port. Input/output mode can be specified bit-wise. Port 2. 8-bit input/output port. Input/output mode can be specified bit-wise.
P20 P21 P22 P23 P24 P25 P26 P27
I/O
Input
SI1 SO1 SCK1 STB BUSY SI0/SB0/SDA0 SO0/SB1/SDA1 SCK0/SCL
P30 to P32 I/O P33 P34 P35 P36 P37 P40 to P47 I/O
Port 3. 8-bit input/output port. Input/output mode can be specified bit-wise.
Input TI1 TI2
--
-- BEEP -- Port 4. 8-bit input/output port. Input/output mode can be specified in 8-bit units. Test input flag (KRIF) is set to 1 by falling edge detection. Port 5. 8-bit input/output port. Input/output mode can be specified bit-wise. Port 6. 8-bit input/output port. Input/output mode can be specified bit-wise. Middle voltage N-ch open drain input/output port. LEDs can be driven directly. Input --
P50 to P57 I/O
Input
--
P60 to P63 I/O P64 to P67
Input
--
P120 to P125
I/O
Port 12. 6-bit input/output port. Input/output mode can be specified bit-wise. Port 13. 3-bit output port. N-ch open-drain output port.
Input
--
P132 to P134
Output
--
PWM0 to PWM2
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PD178004A, 178006A, 178016A, 178018A
3.2 PINS OTHER THAN PORT PINS
Pin Name INTP0 to INTP6 SI0 SI1 SO0 SO1 SB0 SB1 SDA0 SDA1 SCK0 SCK1 SCL STB BUSY TI1 TI2 BEEP Output Output Input Input Serial interface automatic transmit/receive strobe output Serial interface automatic transmit/receive busy input External count clock input to 8-bit timer (TM1) External count clock input to 8-bit timer (TM2) Buzzer output A/D converter analog input PWM output Error out output from charge pump of the PLL frequency synthesizer Inputs PLL local band frequency (In HF, MF mode) Inputs PLL local band frequency (In VHF mode) Inputs AM intermediate frequency counter Inputs FM intermediate frequency counter System reset input System clock oscillation resonator connection Input Input -- -- -- -- -- -- -- -- -- Oscillation regulator. Connected to GND via a 0.1-F capacitor. CPU power supply regulator. Connected to GND via a 0.1-F capacitor. Positive power supply Ground Positive power supply for port block Ground for port block Positive power supply for PLL Ground for PLL Internally connected. Connected to GND or GNDPORT. -- -- -- -- -- -- -- -- -- Input Input Input I/O Serial interface serial clock input/output Input I/O Serial interface serial data input/output Input Output Serial interface serial data output Input I/O Input Function External maskable interrupt inputs with specifiable valid edges (rising edge, falling edge, both rising and falling edges). Serial interface serial data input After Reset Alternate Function Input P00 to P06
Input
Input
P25/SB0/SDA0 P20 P26/SB1/SDA1 P21 P25/SI0/SDA0 P26/SO0/SDA1 P25/SI0/SB0 P26/SO0/SB1 P27/SCL P22 P27/SCK0 P23 P24 P33 P34 P36 P10 to P15 P132 to P134 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
ANI0 to ANI5 Input PWM0 to PWM2 EO0, EO1 VCOL VCOH AMIFC FMIFC RESET X1 X2 REGOSC REGCPU VDD GND VDDPORT GNDPORT VDDPLL Note GNDPLL Note IC Output Output Input Input Input Input Input Input -- -- -- -- -- -- -- -- -- --
Note
Connect a capacitor of approximately 1 000 pF between the VDDPLL pin and GNDPLL pin.
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PD178004A, 178006A, 178016A, 178018A
3.3 INPUT/OUTPUT CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
Table 3-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. Refer to Figure 3-1 for the configuration of the input/output circuit of each type. Table 3-1. I/O Circuit Type of Each Circuit
Pin Name P00/INTP0 P01/INTP1 to P06/INTP6 P10/ANI0 to P15/ANI5 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P30 to P32 P33/TI1, P34/TI2 P35 P36/BEEP P37 P40 to P47 P50 to P57 P60 to P63 P64 to P67 P120 to P125 P132/PWM0 to P134/PWM2 EO0 EO1 VCOL, VCOH AMIFC, FMIFC IC -- -- Connected to GND or GNDPORT directly 19 DTS-EO1 DTS-EO3 DTS-AMP
Note
I/O Circuit Type 2 8 11-A 8 5 8 5 8 10
I/O Input I/O
Recommended Connections of Unused Pins Connected to GND or GNDPORT Set in general-purpose input port mode by software and individually connected to VDD, VDDPORT, GND, or GNDPORT via resistor.
5 8 5
5-G 5 13-D 5
Output
Set to low-level output by software and open Open
Input
Set to disabled status by software and open
Note
For the PD178004A and 178006A, the I/O circuit type is DTS-EO1.
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PD178004A, 178006A, 178016A, 178018A
Figure 3-1. Pin Input/Output Circuit of List (1/2)
Type 2
Type 8
VDD IN data P-ch IN/OUT output disable Schmitt-Triggered Input with Hysteresis Characteristics N-ch
Type 5
Type 10
VDD data P-ch IN/OUT output disable N-ch open-drain output disable data
VDD P-ch IN/OUT N-ch
input enable
Type 5-G
Type 11-A
VDD data P-ch IN/OUT output disable N-ch
VDD data P-ch IN/OUT output disable comparator + _ N-ch VREF (Threshold voltage) input enable N-ch P-ch
Remark All VDD and GND in the above figures are the positive power supply and ground potential of the ports, and should be read as VDDPORT and GNDPORT, respectively.
12
PD178004A, 178006A, 178016A, 178018A
Figure 3-1. Pin Input/Output Circuit of List (2/2)
Type 13-D IN/OUT data output disable
Type DTS-EO3
VDDPLL N-ch DW VDD OUT RD P-ch UP N-ch GNDPLL Middle-Voltage Input Buffer P-ch
Type 19
Type DTS-AMP
VDDPLL OUT N-ch IN
Type DTS-EO1
VDDPLL DW P-ch OUT UP N-ch GNDPLL
Remark All VDD and GND in the above figures are the positive power supply and ground potential of the ports, and should be read as VDDPORT and GNDPORT, respectively.
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PD178004A, 178006A, 178016A, 178018A
4. MEMORY SPACE
Figure 4-1 shows the PD178004A, 178006A, 178016A, and 178018A memory map. Figure 4-1. Memory Map
FFFFH Special Function Registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH
General-Purpose Registers 32 x 8 bits
FABFH Use Prohibited F800H F7FFH Internal Expanded RAM 2 048 x 8 bits F000H EFFFH Use Prohibited Note 2
Note 1
Internal High-Speed RAM 1 024 x 8 bits FB00H FAFFH Use Prohibited Data Memory Space FAE0H FADFH Buffer RAM 32 x 8 bits FAC0H FABFH
nnnnH + 1 nnnnH Program Area 1000H 0FFFH CALLF Entry Area 0800H 07FFH Program Area 0080H 007FH
Use Prohibited
nnnnH + 1 nnnnH Program Memory Space 0000H 0040H 003FH
CALLT Table Area
Internal ROM
Note 3
Vectored Table Area 0000H
Notes 1. Available only for PD178016A and 178018A 2. The PD178018A does not contain this use prohibited area. 3. The internal ROM capacity depends on the version (see the table below).
Corresponding Product Name Internal ROM Last Address nnnnH 7FFFH BFFFH EFFFH
PD178004A PD178006A, 178016A PD178018A
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PD178004A, 178006A, 178016A, 178018A
5. PERIPHERAL HARDWARE FUNCTION FEATURES 5.1 PORTS
The following 3 types of I/O ports are available. * CMOS input (P00) :1 * CMOS input/output (P01 to P06, port 1 to port 5, P64 to P67, port 12) : 54 * N-channel open-drain input/output (P60 to P63) :4 * N-ch open drain output (Port 13) :3 Total : 62 Table 5-1. Port Functions
Name Port 0
Pin Name P00 P01 to P06 Dedicated input port pins
Function
Input/output port pins. Input/output specifiable bit-wise. Input/output port pins. Input/output specifiable bit-wise. Input/output port pins. Input/output specifiable bit-wise. Input/output port pins. Input/output specifiable bit-wise. Input/output port pins. Input/output specifiable in 8-bit units. Test flag (KRIF) is set to 1 by falling edge detection. Input/output port pins. Input/output specifiable bit-wise. N-channel open-drain input/output port pins. Input/output specifiable bit-wise. LED direct drive capability. Input/output port pins. Input/output specifiable bit-wise. Input/output port pins. Input/output specifiable bit-wise. N-ch open drain output port.
Port 1 Port 2 Port 3 Port 4 Port 5 Port 6
P10 to P15 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P63 P64 to P67
Port 12 Port 13
P120 to P125 P132 to P134
15
PD178004A, 178006A, 178016A, 178018A
5.2 CLOCK GENERATOR
The instruction execution time can be changed as follows. 0.44 s/0.88 s/1.78 s/3.56 s/7.11 s/14.22 s (@ 4.5-MHz crystal oscillator with system clock.) Figure 5-1. Clock Generator Block Diagram
Prescaler X1 X2
Clock to the PLL frequency synthesizer, basic timer and buzzer output control circuit.
System Clock Oscillator
fX Selector Scaler fXX Prescaler fXX fXX fXX 2 22 23 fXX 24 Selector Standby Control Circuit
Clock to peripheral hardware other than the above.
STOP
fX 2
Wait Control Circuit
CPU Clock (fCPU)
To INTP0 Sampling Clock
5.3 TIMER
The PD178004A, 178006A, 178016A, and 178018A incorporate 5 channels of the timer. * Basic timer : 1 channel * 8-bit timer/event counter : 2 channels * 8-bit timer (D/A converter) Note : 1 channel * Watchdog timer : 1 channel Note Used is shared with the 8/9-bit resolution x 3-channel D/A converter (PWM output). Figure 5-2. Basic Timer Block Diagram
4.5 MHz
Divider
INTTMC
16
PD178004A, 178006A, 178016A, 178018A
Figure 5-3. 8-Bit Timer/Event Counter Block Diagram
Internal Bus INTTM1 8-Bit Compare Register (CR10)
8-Bit Compare Register (CR20) Selector Match INTTM2
Match fxx/2 to fxx/2 9 fx/2 11 TI1/P33 Selector 8-Bit Timer Register 1 (TM1) Selector Clear 8-Bit Timer Register 2 (TM2) Clear Selector Selector
fxx/2 to fxx/2 9 fx/2 11 TI2/P34
Internal Bus
Figure 5-4. 8-Bit Timer (D/A Converter) Block Diagram
Internal Bus INTPWM PWM Data Register 2 Note (PWMR2) 4.5 MHz PWM Duty Setting Block PWM Data Register 1 (PWMR1) PWM Data Register 0 (PWMR0) PWM Mode Select Register PWM PWM PWM 0SE 1SE 2SE
Clock Generation Block
Comparator
Comparator
Comparator
Output Select Block Output Select Block
P132/PWM0
Clear Circuit
P133/PWM1
fPWM
b8
9-Bit Binary Counter
b0
Output Select Block
P134/PWM2
PWM PWM PWM PWM PWM BIT CK0 MD ST RES PWM Control Register Internal Bus
Note
The PWM data register 2 (PWMR2) is multiplexed with the PWM timer register (PWMTMR).
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PD178004A, 178006A, 178016A, 178018A
Figure 5-5. Watchdog Timer Block Diagram
f xx 23
Prescaler
f xx 24
f xx 25
f xx 26
f xx 27
f xx 28
f xx 29
f xx 2 11
INTWDT Maskable Interrupt Request Selector 8-Bit Counter Control Circuit Reset INTWDT Non-Maskable Interrupt Request
5.4 BUZZER OUTPUT CONTROL CIRCUIT
The clock with the following frequency can be output as a buzzer output. * 1.5 kHz/3 kHz/6 kHz (@ 4.5-MHz crystal oscillator with system clock) Figure 5-6. Buzzer Output Control Circuit Block Diagram
3 kHz 6 kHz
Selector
1.5 kHz
BEEP/P36
3
TCL27 TCL26 TCL25 Timer Clock Select Register 2
P36 Output Latch
PM36 Port Mode Register 3
Internal Bus
18
PD178004A, 178006A, 178016A, 178018A
5.5 A/D CONVERTER
An A/D converter of 8-bit resolution x 6 channels is incorporated. The following two types of the A/D conversion operation start-up methods are available. * Hardware start * Software start Figure 5-7. A/D Converter Block Diagram
Resistor String ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 Succesive Approximation Register (SAR) GND Selector Sample & Hold Circuit Voltage Comparator Tap Selector VDD
INTP3/P03
Edge Detection Circuit
Control Circuit
INTAD INTP3
A/D Conversion Result Register (ADCR)
Internal Bus
5.6 SERIAL INTERFACES
2 channels of the clocked serial interface are incorporated. * Serial interface channel 0 * Serial interface channel 1 Table 5-2. Types and Functions of Serial Interface
Function 3-wire serial I/O mode 3-wire serial I/O mode with automatic transmission/ reception function SBI (serial bus interface) mode 2-wire serial I/O mode I2C Bus Mode (MSB first) (MSB first) (MSB first) Serial Interface Channel 0 (MSB/LSB first switchable) Serial Interface Channel 1 (MSB/LSB first switchable) (MSB/LSB first switchable)
--
-- -- --
19
PD178004A, 178006A, 178016A, 178018A
Figure 5-8. Serial Interface Channel 0 Block Diagram
Internal Bus
SI0/SB0/SDA0/P25 Selector SO0/SB1/SDA1/P26 Serial I/O Shift Register 0 (SIO0) Output Latch
Selector
Bus Release/Command/ Acknowledge Detection Circuit Serial Clock Counter
Busy/Acknowledge Output Circuit
SCK0/SCL/P27
Interrupt Request Signal Generator
INTCSI0
fXX/2 to fXX/2 8 Serial Clock Control Circuit Selector
Figure 5-9. Serial Interface Channel 1 Block Diagram
Internal Bus
Automatic Data Transmit/ Receive Address Pointer (ADTP)
Buffer RAM
Automatic Data Transmit/Receive Interval Specification Register (ADTI) Match
SI1/P20
Serial I/O Shift Register 1 (SIO1)
SO1/P21 5-Bit Counter STB/P23 Handshake Control Circuit
BUSY/P24
SCK1/P22
Serial Counter
Interrupt Request Signal Generator
INTCSI1
f XX/2 to f XX/2 8 Serial Clock Control Circuit Selector
20
PD178004A, 178006A, 178016A, 178018A
5.7 PLL FREQUENCY SYNTHESIZER
Figure 5-10. PLL Frequency Synthesizer Block Diagram
Internal Bus PLL Mode Select Register PLL PLL MD1 MD0 2 VCOH Mixer VCOL Input Select Block Programmable Divider PLL Data Register (PLLRL, PLLRH, PLLR0) 2 fN Phase Comparator ( -DET) Charge Pump EO0 EO1 PLL NS0 PWM Data Transfer Register
fr
Voltage Control Generator
Note
4.5 MHz
Reference Frequency Generator
Unlock FF
4
Note
Low pass Filter
PLL PLL PLL PLL RF3 RF2 RF1 RF0 PLL Reference Mode Register PLL Unlock FF Judge Register Internal Bus
PLL UL0
EOC EOC ON1 ON0 EO Select Register
Note
External circuit
Cautions 1. Be sure to set EOCON0 to 0. 2. For the PD178004A and 178006A, do not set EOCON1 to 1.
21
PD178004A, 178006A, 178016A, 178018A
5.8 FREQUENCY COUNTER
Figure 5-11. Frequency Counter Block Diagram
2
Gate Time Control Block
FMIFC Input Select Block AMIFC
Start/Stop Control Block
IF Counter Register (IFC) Block
2
IFC IFC IFC IFC MD1 MD0 CK1 CK0 IF Counter Mode Select Register
IFC JG0 IF Counter Gate Judge Register Internal Bus
IFC IFC ST RES IF Counter Control Register
22
PD178004A, 178006A, 178016A, 178018A
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS 6.1 INTERRUPT FUNCTIONS
Interrupt functions include three types and 17 sources, as shown below. * Non-maskable: 1 * Maskable : 15 * Software :1 Table 6-1. Interrupt Source List
Note 1
Interrupt Type Nonmaskable Maskable
Default Priority --
Interrupt Source Name INTWDT Trigger Watchdog timer overflow (watchdog timer mode 1 selected) Watchdog timer overflow (interval timer mode selected) Pin input edge detection
Internal/ External Internal
Basic Vector Table Configuration Address Type Note 2 0004H (A)
0
INTWDT
(B)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 Software --
INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTCSI0 INTCSI1 INTTMC INTPWM INTTM1
External
0006H 0008H 000AH 000CH 000EH 0010H 0012H
(C) (D)
End of serial interface channel 0 transfer End of serial interface channel 1 transfer Generation of match signal of basic timer Generation of match signal of 8-bit timer Generation of match signal of 8-bit timer/ event counter 1 Generation of match signal of 8-bit timer/ event counter 2 End of conversion by A/D converter BRK instruction execution
Internal
0014H 0016H 0018H 001AH 001CH
(B)
INTTM2 INTAD BRK
001EH 0020H Internal 003EH (E)
Notes 1. The default priority is a priority order when two or more maskable interrupts are generated simultaneously. 0 is the highest order and 14, the lowest. 2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1, respectively.
23
PD178004A, 178006A, 178016A, 178018A
Figure 6-1. Interrupt Function Basic Configuration (1/2) (A) Internal non-maskable interrupt
Internal Bus
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
(B) Internal maskable interrupt
Internal Bus
MK
IE
PR
ISP
Interrupt Request
IF
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
(C) External maskable interrupt (INTP0)
Internal Bus
Sampling Clock Select Register (SCS)
External Interrupt Mode Register (INTM0)
MK
IE
PR
ISP
Interrupt Request
Sampling Clock
Edge Detection Circuit
IF
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
24
PD178004A, 178006A, 178016A, 178018A
Figure 6-1. Interrupt Function Basic Configuration (2/2) (D) External maskable interrupt (except INTP0)
Internal Bus
External Interrupt Mode Register (INTM0, INTM1)
MK
IE
PR
ISP
Interrupt Request
Edge Detection Circuit
IF
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
(E) Software interrupt
Internal Bus
Interrupt Request
Priority Control Circuit
Vector Table Address Generator
IF : IE : ISP : MK : PR :
Interrupt request flag Interrupt enable flag In-service priority flag Interrupt mask flag Priority specification flag
25
PD178004A, 178006A, 178016A, 178018A
6.2 TEST FUNCTION
A test function with a single source is provided, as shown in Table 6-2. Table 6-2. Test Input Source List
Test Input Source Internal/External Name INTPT4 Trigger Port 4 falling edge detection External
Figure 6-2. Test Function Basic Configuration
Internal Bus
MK
Test Input
IF
Standby Release Signal
IF : Test input flag MK : Test mask flag
26
PD178004A, 178006A, 178016A, 178018A
7. STANDBY FUNCTION
There are the following two standby functions to reduce the system power consumption. * HALT mode : The CPU operating clock is stopped. The average consumption current can be reduced by intermittent operation in combination with the normal operating mode. * STOP mode : The system clock oscillation is stopped. All operations by the system clock are stopped and current consumption can be considerably reduced. Figure 7-1. Stand-by Function
System Clock Operation STOP Instruction Interrupt Request HALT Mode (Clock supply to CPU is stopped, oscillation continued) HALT Instruction
Interrupt Request
STOP Mode (System clock oscillation stopped)
8. RESET FUNCTION
There are the following three reset methods. * External reset input by RESET pin * Internal reset by watchdog timer runaway time detection * Internal reset by Power-On Clear (POC).
27
PD178004A, 178006A, 178016A, 178018A
9. INSTRUCTION SET
(1) 8-bit instructions MOV, XCH, ADD ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second Operand First Operand A #byte A
[HL + byte]
r Note
sfr
saddr
!addr16
PSW
[DE]
[HL]
[HL + B] [HL + C]
$addr16
1
None
ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV
MOV XCH
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
ROR ROL RORC ROLC
r
MOV
INC DEC
B,C sfr saddr MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV
DBNZ
DBNZ
INC DEC
!addr16 PSW [DE] [HL] [HL + byte] [HL + B] [HL + C] X C MOV
MOV MOV PUSH POP ROR4 ROL4
MOV MOV
MULU DIVUW
Note
Except r = A
28
PD178004A, 178006A, 178016A, 178018A
(2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand First Operand AX #word ADDW SUBW CMPW MOVW MOVW Note AX rp Note MOVW XCHW sfrp MOVW saddrp MOVW !addr16 MOVW SP MOVW None
rp
INCW DECW PUSH POP
sfrp saddrp !addr16 SP
MOVW MOVW MOVW
MOVW MOVW MOVW MOVW
Note
Only when rp = BC, DE or HL
(3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second Operand First Operand A.bit A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY MOV1 $addr16 BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR None SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 NOT1
sfr.bit
MOV1
saddr.bit
MOV1
PSW.bit
MOV1
[HL].bit
MOV1
CY
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
(4) Call instruction/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second Operand First Operand Basic instruction Compound instruction BR AX !addr16 CALL BR !addr11 CALLF [addr5] CALLT $addr16 BR, BC, BNC BZ, BNZ BT, BF BTCLR DBNZ
(5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
29
PD178004A, 178006A, 178016A, 178018A
10. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25 C)
Parameter Power supply voltage Input voltage Symbol VDD VI1 VI2 Output voltage Output withstand voltage Analog input voltage Output current high VO VBDS P132 to P134 N-ch Open-drain Excluding P60 to P63 P60 to P63 N-ch Open-drain Test Conditions Rating -0.3 to + 7.0 -0.3 to VDD + 0.3 -0.3 to +16 -0.3 to VDD + 0.3 16 Unit V V V V V
VAN IOH
P10 to P15 1 pin
Analog input pin
-0.3 to VDD + 0.3 -10 -15
V mA mA
P01 to P06, P30 to P37, P56, P57, P60 to P67, P120 to P125 total P10 to P15, P20 to P27, P40 to P47, P50 to P55, P132 to P134 total Output current low IOL Note 1 pin Peak value Effective value Operating ambient temperature Storage temperature TA
-15
mA
15 7.5 -40 to +85
mA mA C C
Tstg
-65 to +150
Note
Effective value should be calculated as follows: [Effective value] = [Peak value] x duty
Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter even momentarily. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. Remark The characteristics of alternate-function pins and port pins are the same unless specified otherwise. RECOMMENDED SUPPLY VOLTAGE RANGES (TA = -40 to +85 C)
Parameter Power supply voltage Symbol VDD1 VDD2 Test Conditions During CPU operation and PLL operation. While the CPU is operating and the PLL is stopped. Cycle Time: TCY 0.89 s While the CPU is operating and the PLL is stopped. Cycle Time: TCY = 0.44 s MIN. 4.5 3.5 TYP. MAX. 5.5 5.5 Unit V V
VDD3
4.5
5.5
V
Remark TCY: Cycle Time (Minimum instruction execution time)
30
PD178004A, 178006A, 178016A, 178018A
DC CHARACTERISTICS (TA = -40 to +85 C, VDD = 3.5 to 5.5 V) (1/3)
Parameter Input voltage high Symbol VIH1 P10 P30 P40 P64 to to to to P15, P32, P47, P67, Test Conditions P21, P23, P35 to P37, P50 to P57, P120 to P125 MIN. 0.7 VDD TYP. MAX. VDD Unit V
VIH2
P00 to P06, P20, P22, P24 to P27, P33, P34, RESET P60 to P63 (N-ch Open-drain) P10 P30 P40 P64 to to to to P15, P32, P47, P67, P21, P23, P35 to P37, P50 to P57, P120 to P125
0.85 VDD
VDD
V
VIH3
0.7 VDD
15
V
Input voltage low
VIL1
0
0.3 VDD
V
VIL2
P00 to P06, P20, P22, P24 to P27, P33, P34, RESET P60 to P63 (N-ch Open-drain) 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V 4.5 V VDD 5.5 V IOH = -1 mA 3.5 V VDD < 4.5 V IOH = -100 A
0
0.15 VDD
V
VIL3
0 0 VDD - 1.0
0.3 VDD 0.2 VDD
V V V
Output voltage high
VOH1
VDD - 0.5
V
Output voltage low
VOL1
P50 to P57, P60 to P63
VDD = 4.5 to 5.5 V, IOH = 15 mA VDD = 4.5 to 5.5 V, IOL = 1.6 mA
0.4
2.0
V
P01 to P06, P10 to P15, P20 to P27, P30 to P37, P40 to P47, P64 to P67, P120 to P125, P132 to P134 VOL2 SB0, SB1, SCK0
0.4
V
VDD = 4.5 to 5.5 V, open-drain pulled-up (R = 1 K)
0.2 VDD
V
Remark The characteristics of alternate-function pins and port pins are the same unless specified otherwise.
31
PD178004A, 178006A, 178016A, 178018A
DC CHARACTERISTICS (TA = -40 to +85 C, VDD = 3.5 to 5.5 V)
Parameter Input leakage current high Symbol ILIH1 P00 to P06, P20 to P27, P40 to P47, P64 to P67, RESET P60 to P63 P00 to P06, P20 to P27, P40 to P47, P64 to P67, RESET P60 to P63 P132 to P134 VOUT = 15 V P10 to P15, P30 to P37, P50 to P57, P120 to P125, Test Conditions P10 to P15, P30 to P37, P50 to P57, P120 to P125, VIN = VDD MIN. TYP. MAX. 3
(2/3)
Unit
A
ILIH2 Input leakage current low ILIL1
VIN = 15 V VIN = 0 V
80 -3
A A
ILIL2 Output leakage current high Output leakage current low Output off leak current ILOH
-3 Note 3
A A A A
ILOL
P132 to P134
VOUT = 0 V
-3 1
ILOF
EO0, EO1
VOUT = VDD, VOUT = 0 V
Note
When an input instruction is executed, the low-level input leakage current for P60 to P63 becomes -200 A (MAX.) only in one clock cycle (at no wait). It remains at -3 A (MAX.) for other than an input instruction.
Remark The characteristics of alternate-function pins and port pins are the same unless specified otherwise. REFERENCE CHARACTERISTICS (TA = 25 C, VDD = 5 V)
Parameter Output current high Symbol IOH1 EO0 EO1 (EOCON0 = 0) Output current low IOL1 EO0 EO1 (EOCON0 = 0) VOUT = 1 V 3.5 Test Conditions VOUT = VDD - 1 V -1.8 6 MIN. TYP. -4 MAX.
(1/2)
Unit mA mA mA mA
32
PD178004A, 178006A, 178016A, 178018A
DC CHARACTERISTICS (TA = -40 to +85 C, VDD = 3.5 to 5.5 V)
Parameter Power Supply Current IDD2
Note 1
(3/3)
MIN.
Note 2
Symbol IDD1
Test Conditions While the CPU is operating and the PLL is stopped fX = 4.5 MHz operation TCY = 0.89 s
TYP. 2.5
MAX. 15
Unit mA
TCY = 0.44 s Note 3 VDD = 4.5 to 5.5 V TCY = 0.89 s Note 2
4.0
27
mA
IDD3
IDD4
While the CPU is operating and the PLL is stopped HALT Mode Pin X1 sine wave input VIN = VDD. fX = 4.5 MHz operation When the crystal is oscillating
0.7
1.5
mA
TCY = 0.44 s Note 3 VDD = 4.5 to 5.5 V TCY = 0.44 s TCY = 0.89 s
1.0
2.0
mA
Data Hold Power Supply Voltage
VDR1 VDR2 VDR3
4.5 3.5 2.6
5.5 5.5 5.5
V V V
When the crystal oscillator is stopped When power off by Power On Clear is detected While the crystal oscillator is stopped TA = 25 C, VDD = 5V
Data Hold Power Supply Current
IDR1 IDR2
2 2
4 30
A A
Notes 1. The port current is not included. 2. When the Processor Clock Control register (PCC) is set at 00H, and the Oscillation Mode Select register (OSMS) is set at 00H. 3. When PCC is set at 00H and OSMS is set at 01H. Remarks 1. TCY: Cycle Time (Minimum instruction execution time) 2. fx: System clock oscillator frequency. REFERENCE CHARACTERISTICS (TA = 25 C, VDD = 5 V)
Parameter Power Supply Current Symbol IDD5 Test Conditions During CPU operation and PLL operation. VCOH pin sine wave input fIN = 130 MHz, VIN = 0.15 Vp-p TCY = 0.44 s
Note
(2/2)
MIN. TYP. 7 MAX. Unit mA
Note
When the Processor Clock Control register (PCC) is set at 00H, and the Oscillation Mode Select register (OSMS) is set at 01H.
Remark TCY: Cycle Time (Minimum instruction execution time)
33
PD178004A, 178006A, 178016A, 178018A
AC CHARACTERISTICS (1) BASIC OPERATION (TA = -40 to +85 C, VDD = 3.5 to 5.5 V)
Parameter Cycle time (Minimum instruction execution time) TI1, TI2 input frequency TI1, TI2 input high/ low-level width Interrupt input high/ low-level width RESET low level width tTIH, tTIL TINTH, TINTL tRSL fTI Symbol TCY fXX = fX/2 fXX = fX
Note 1
Test Conditions , fX = 4.5 MHz operation 4.5 VDD 5.5 V 3.5 VDD < 4.5 V
MIN. 0.89 0.44 0.89 0 0 111 1.8 8/fsam
Note 3
TYP.
MAX. 14.22 7.11 7.11 4.5 275
Unit
s s s
MHz kHz ns
Note 2
,
fX = 4.5 MHz operation 4.5 VDD 5.5 V 3.5 V VDD 4.5 V 4.5 VDD 5.5 V 3.5 V VDD 4.5 V INTP0 INTP1 to INTP6
s s s s
10 10
Notes 1. When oscillation mode selection (OSMS) register is set at 00H. 2. When OSMS is set at 01H. 3. In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register (SCS), selection of fsam is possible between fXX/2 N, fXX/32, fXX/64 and fXX/128 (when N = 0 to 4). Remarks 1. fXX: System clock frequency (fX or fX/2) 2. fX: System clock oscillation frequency TCY vs VDD (At FXX = FX/2 system clock operation) TCY vs VDD (At FXX = FX system clock operation)
60
60
10 Cycle Time TCY [s] Operation Guaranteed Range 2.0 1.0 0.5 0.4 Cycle Time TCY [s]
10
2.0 1.0 0.5 0.4
Operation Guaranteed Range
0 1 2 3 4 5 6 Power Supply Voltage VDD [V]
0 1 2 3 4 5 6 Power Supply Voltage VDD [V]
34
PD178004A, 178006A, 178016A, 178018A
(2) SERIAL INTERFACE (TA = -40 to +85 C, VDD = 3.5 to 5.5 V) (a) Serial interface channel 0 (i) 3-wire serial I/O mode (SCK0 ... internal clock output)
Parameter SCK0 cycle time Symbol tKCY1 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SCK0 high-/low-level width tKH1, tKL1 SI0 setup time (to SCK0) tSIK1 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SI0 hold time (from SCK0) SO0 output delay time from SCK0 tKSI1 tKSO1 C = 100 pF
Note
MIN. 800 1 600 tKCY1/2 - 50 tKCY1/2 - 100 100 150 400
TYP.
MAX.
Unit ns ns ns ns ns ns ns
300
ns
Note
C is the load capacitance of SO0 output line. (ii) 3-wire serial I/O mode (SCK0 ... external clock input)
Parameter Symbol tKCY2 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V MIN. 800 1 600 400 800 100 400 C = 100 pF Note 300 1 000 TYP. MAX. Unit ns ns ns ns ns ns ns ns
SCK0 cycle time
SCK0 high-/low-level width
tKH2, tKL2
4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V
SI0 setup time (to SCK0) SI0 hold time (from SCK0) SO0 output delay time from SCK0 SCK0 at rising or falling edge time
tSIK2 tKSI2 tKSO2 tR2, tF2
Note
C is the load capacitance of SO0 output line.
35
PD178004A, 178006A, 178016A, 178018A
(iii) SBI mode (SCK0 ... internal clock output)
Parameter SCK0 cycle time Symbol tKCY3 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SCK0 high-/low-level width tKH3, tKL3 SB0, SB1 setup time (to SCK0) tSIK3 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width tKSB tSBK tSBH tSBL tKSI3 tKSO3 R = 1 k 4.5 V VDD 5.5 V MIN. 800 3 200 tKCY3/2 - 50 tKCY3/2 - 150 100 300 tKCY3/2 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1 000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
C = 100 pF Note 3.5 V VDD < 4.5 V
Note R and C are the load resistance and load capacitance of SB0 and SB1 output line. (iv) SBI mode (SCK0 ... external clock input)
Parameter SCK0 cycle time Symbol tKCY4 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SCK0 high-/low-level width tKH4, tKL4 SB0, SB1 setup time (to SCK0) tSIK4 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width SCK0 at rising or falling edge time tKSB tSBK tSBH tSBL tR4, tF4 tKSI4 tKSO4 R = 1 k 4.5 V VDD 5.5 V MIN. 800 3 200 400 1 600 100 300 tKCY4/2 0 0 tKCY4 tKCY4 tKCY4 tKCY4 1 000 300 1 000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
C = 100 pF Note 3.5 V VDD < 4.5 V
Note
R and C are the load resistance and load capacitance of SB0 and SB1 output line.
36
PD178004A, 178006A, 178016A, 178018A
(v) 2-wire serial I/O mode (SCK0 ... internal clock output)
Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width Symbol tKCY5 tKH5 tKL5 Test Conditions R = 1 k C = 100 pF
Note
MIN. 1 600 tKCY5/2 - 160
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns
4.5 V VDD 5.5 V tKCY5/2 - 50 3.5 V VDD < 4.5 V tKCY5/2 - 100
SB0, SB1 setup time (to SCK0)
tSIK5
4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V
300 350 400
SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0
tKSI5 tKSO5
600 0 300
ns
Note
R and C are the load resistance and load capacitance of SCK0, SB0 and SB1 output line. (vi) 2-wire serial I/O mode (SCK0 ... external clock input)
Parameter Symbol tKCY6 tKH6 tKL6 tSIK6 tKSI6 tKSO6 R = 1 k C = 100 pF tR6, tF6
Note
Test Conditions
MIN. 1 600 650 800 100 tKCY6/2
TYP.
MAX.
Unit ns ns ns ns ns
SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SCK0 at rising or falling edge time
4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V
0 0
300 500 1 000
ns ns ns
Note
R and C are the load resistance and load capacitance of SB0 and SB1 output line.
37
PD178004A, 178006A, 178016A, 178018A
(vii) I2C Bus mode (SCL ... internal clock output)
Parameter SCL cycle time SCL high-level width SCL low-level width SDA0, SDA1 setup time (to SCL) SDA0, SDA1 hold time (from SCL) SDA0, SDA1 output delay time (from SCL) SDA0, SDA1 from SCL or SDA0, SDA1 from SCL SCL from SDA0, SDA1 SDA0, SDA1 high-level width Symbol tKCY7 tKH7 tKL7 tSIK7 tKSI7 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V tKSB 0 Test Conditions R = 1 k C = 100 pF Note MIN. 10 tKCY7 - 160 tKCY7 - 50 200 ns TYP. MAX. Unit
s
ns ns ns
tKSO7
0 0 200
300 500
ns ns ns
tSBK tSBH
400 500
ns ns
Note
R and C are the load resistance and load capacitance of SCL, SDA0 and SDA1 output line. (viii) I 2C Bus mode (SCL ... external clock input)
Parameter Symbol tKCY8 tKH8, tKL8 tSIK8 tKSI8 4.5 V VDD 5.5 V 0 Test Conditions MIN. 1 000 400 200 ns TYP. MAX. Unit ns ns ns
SCL cycle time SCL high-/low-level width SDA0, SDA1 setup time (to SCL) SDA0, SDA1 hold time (from SCL) SDA0, SDA1 output delay time from SCL SDA0, SDA1 from SCL or SDA0, SDA1 from SCL SCL from SDA0, SDA1 SDA0, SDA1 high-level width SCL at rising or falling edge time
tKSO8
R = 1 k
0 0 200
300 500
ns ns ns
C = 100 pF Note 3.5 V VDD < 4.5 V tKSB
tSBK tSBH tR8, tF8
400 500 1 000
ns ns ns
Note
R and C are the load resistance and load capacitance of SDA0 and SDA1 output line.
38
PD178004A, 178006A, 178016A, 178018A
(b) Serial interface channel 1 (i) 3-wire serial I/O mode (SCK1 ... internal clock output)
Parameter SCK1 cycle time Symbol tKCY9 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SCK1 high/low-level width tKH9, tKL9 SI1 setup time (to SCK1) tSIK9 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SI1 hold time (from SCK1) SO1 output delay time (from SCK1) tKSI9 tKSO9 C = 100 pF
Note
MIN. 800 1 600 tKCY9/2 - 50 tKCY9/2 - 100 100 150 400
TYP.
MAX.
Unit ns ns ns ns ns ns ns
300
ns
Note
C is the load capacitance of SO1 output line. (ii) 3-wire serial I/O mode (SCK1 ... external clock input)
Parameter Symbol tKCY10 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V MIN. 800 1 600 400 800 100 400 C = 100 pF Note 300 1 000 TYP. MAX. Unit ns ns ns ns ns ns ns ns
SCK1 cycle time
SCK1 high/low-level width
tKH10, tKL10
4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V
SI1 setup time (to SCK1) SI1 hold time (from SCK1) SO1 output delay time (from SCK1)
tSIK10 tKSI10 tKSO10
SCK1 at rising or falling edge time tR10, tF10
Note
C is the load capacitance of SO1 output line.
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PD178004A, 178006A, 178016A, 178018A
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... internal clock output)
Parameter SCK1 cycle time Symbol tKCY11 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SCK1 high/low-level width tKH11, tKL11 SI1 setup time (to SCK1) tSIK11 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SI1 hold time (from SCK1) SO1 output delay time (from SCK1) STB from SCK1 Strobe signal high-level width Busy signal setup time (to busy signal detection timing) Busy signal hold time (from busy signal detection timing) SCK1 from busy inactive tSPS tKSI11 tKSO11 tSBD tSBW tBYS 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V C = 100 pF Note tKCY11/2 - 100 tKCY11/ - 30 100 MIN. 800 1 600 tKCY11/2 - 50 tKCY11/2 - 100 100 150 400 300 tKCY11/2 + 100 tKCY11 + 30 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
tBYH
100 150 2tKCY11
ns ns ns
Note
C is the load capacitance of SO1 output line. (iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... external clock input)
Parameter Symbol tKCY12 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V MIN. 800 1 600 400 800 100 400 C = 100 pF Note 300 1 000 TYP. MAX. Unit ns ns ns ns ns ns ns ns
SCK1 cycle time
SCK1 high/low-level width
tKH12, tKL12
4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V
SI1 setup time (to SCK1) SI1 hold time (from SCK1) SO1 output delay time (from SCK1)
tSIK12 tKSI12 tKSO12
SCK1 at rising or falling edge time tR12, tF12
Note
C is the load capacitance of SO1 output line.
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PD178004A, 178006A, 178016A, 178018A
AC TIMING TEST POINT (EXCLUDING X1 INPUT)
0.8 VDD 0.2 VDD
Test Points
0.8 VDD 0.2 VDD
TI Timing
1/fTI
tTIL
tTIH
TI1, TI2
Interrupt Input Timing
tINTL
tINTH
INTP0 to INTP6
RESET Input Timing
tRSL
RESET
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PD178004A, 178006A, 178016A, 178018A
SERIAL TRANSFER TIMING 3-Wire Serial I/O Mode:
tKCYm tKLm tRn SCK0, SCK1 tSIKm tKSIm tKHm tFn
SI0, SI1 tKSOm
Input Data
SO0, SI1
Output Data
Remark m = 1, 2, 9, 10 n = 2, 10 SBI Mode (Bus Release Signal Transfer):
tKCY3, 4 tKL3, 4 tR4 SCK0 tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4 tKH3, 4 tF4
SB0, SB1 tKSO3, 4
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PD178004A, 178006A, 178016A, 178018A
SBI Mode (Command Signal Transfer):
tKCY3, 4 tKL3, 4 tR4 tKH3, 4 tF4
SCK0 tSIK3, 4 tKSB tSBK tKSI3, 4
SB0, SB1 tKSO3, 4
2-Wire Serial I/O Mode:
tKCY5, 6 tKL5, 6 tR6 SCK0 tSIK5, 6 tKSO5, 6 SB0, SB1 tKSI5, 6 tKH5, 6 tF6
I2C Bus Mode:
tF8 SCL tKL7, 8
tR8
tKCY7, 8 tSIK7, 8 tKSO7, 8 tKSB tSBK tKSB
tKSI7, 8
tKH7, 8
SDA0, SDA1 tSBH tSBK
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PD178004A, 178006A, 178016A, 178018A
3-Wire Serial I/O Mode with Automatic Transmit/Receive Function:
SO1
D2
D1
D0
D7
SI1
D2 tSIK11, 12 tKSO11, 12
D1
D0 tKSI11, 12 tKH11, 12 tF12
D7
SCK1 tR12 tKL11, 12 STB tKCY11, 12 tSBD tSBW
3-Wire Serial I/O Mode with Automatic Transmit/Receive Function (Busy Processing):
SCK1
7
8
9 Note
10 Note tBYS
10 + n Note tBYH tSPS
1
BUSY (Active high)
Note
The signal is not actually driven low here; it is shown as such to indicate the timing.
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PD178004A, 178006A, 178016A, 178018A
A/D CONVERTER CHARACTERISTICS (TA = -40 to +85 C, VDD = 4.5 to 5.5 V)
Parameter Resolution Conversion total error Conversion time Sampling time Analog input voltage tCONV tSAMP VIAN 22.2 15/fXX 0 VDD Symbol Test Conditions MIN. 8 TYP. 8 MAX. 8 3.0 44.4 Unit bit LSB
s s
V
Remarks 1. fXX: System clock frequency (fX/2) 2. fX: System clock oscillation frequency PLL CHARACTERISTICS (TA = -40 to +85 C, VDD = 4.5 to 5.5 V)
Parameter Operating Frequency Symbol fIN1 fIN2 fIN3 Test Conditions VCOL Pin MF Mode Sine wave input VIN = 0.1 Vp-p VCOL Pin HF Mode Sine wave input VIN = 0.2 Vp-p VCOH Pin VHF Mode Sine wave input VIN = 0.15 Vp-p MIN. 0.5 9 60 TYP. MAX. 3 55 160 Unit MHz MHz MHz
IFC CHARACTERISTICS (TA = -40 to +85 C, VDD = 4.5 to 5.5 V)
Parameter Operating Frequency fIN5 Symbol fIN4 Test Conditions AMIFC Pin AMIF Count Mode Sine wave input VIN = 0.1 Vp-p Note FMIFC Pin FMIF Count Mode Sine wave input VIN = 0.1 Vp-p Note FMIFC Pin AMIF Count Mode Sine wave input VIN = 0.1 Vp-p Note MIN. 0.4 TYP. MAX. 0.5 Unit MHz
10
11
MHz
fIN6
0.4
0.5
MHz
Note
The condition of a sine wave input of VIN = 0.1 Vp-p is the standard value for operation of this device during stand-alone operation, so in consideration of the effect of noise, it is recommended that operation be at an input amplitude condition of VIN = 0.15 Vp-p.
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PD178004A, 178006A, 178016A, 178018A
11. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14x14)
A B
60 61
41 40
detail of lead end
CD
S Q R
80 1
21 20
F G H P I
M
J K M N L
NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 17.20.4 14.00.2 14.00.2 17.20.4 0.825 0.825 0.300.10 0.13 0.65 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.10 2.7 0.10.1 55 3.0 MAX.
INCHES 0.6770.016 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6770.016 0.032 0.032 0.012 +0.004 -0.005 0.005 0.026 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.0040.004 55 0.119 MAX. S80GC-65-3B9-4
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PD178004A, 178006A, 178016A, 178018A
12. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 12-1. Surface Mounting Type Soldering Conditions
PD178004AGC-xxx-3B9 : 80-pin plastic QFP (14 x 14 mm, 0.65 mm pitch) PD178006AGC-xxx-3B9 : 80-pin plastic QFP (14 x 14 mm, 0.65 mm pitch) PD178016AGC-xxx-3B9 : 80-pin plastic QFP (14 x 14 mm, 0.65 mm pitch) PD178018AGC-xxx-3B9 : 80-pin plastic QFP (14 x 14 mm, 0.65 mm pitch)
Recommended Condition Symbol IR35-00-3
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235 C, Duration: 30 sec. max. (at 210 C or above), Number of times: Three times max. Package peak temperature: 215 C, Duration: 40 sec. max. (at 200 C or above), Number of times: Three times max. Solder bath temperature : 260 C max., Duration : 10 sec. max., Number of times : once, Preheating temperature : 120 C max. (package surface temperature) Pin temperature: 300 C max. Duration: 3 sec. max. (per pin row)
VPS
VP15-00-3
Wave soldering
WS60-00-1
Partial heating
--
Caution Do not use different soldering method together (except for partial heating).
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PD178004A, 178006A, 178016A, 178018A
APPENDIX A. DIFFERENCES BETWEEN PD178018A AND PD178018 SUBSERIES
Product name
PD178018A Subseries
PD178004A PD178006A PD178016A PD178018A PD178P018A Note PD178004
PD178018 Subseries
PD178006 PD178016 PD178018 PD178P018
Item PLL frequency synthesizer Reference frequency EO0 pin output format EO1 pin output format
7 types selectable by program (1, 3, 5, 9, 10, 25, 50 kHz) Buffer type
11 types selectable by program (1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 25, 50 kHz)
Buffer type
Constant-current power supply type
EO1 pin highNot supported impedance function
Supported
Not supported
Note
Under development
Remark The mask ROM of mask versions (PD178018A and PD178018) is replaced with one-time PROM or EPROM in the one-time PROM versions (PD178P018A and PD178P018).
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PD178004A, 178006A, 178016A, 178018A
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD178018A Subseries. Language Processing Software
RA78K/0 Notes 1, 2, 3, 4 CC78K/0
Notes 1, 2, 3, 4 Notes 1, 2, 3, 4, 8 Notes 1, 2, 3, 4
78K/0 Series common assembler package 78K/0 Series common C compiler package
DF178018
PD178018A Subseries common device file
78K/0 Series common C compiler library source file
CC78K/0-L
PROM Writing Tools
PG-1500 PG-178P018GC PA-178P018KK-T PG-1500 controller Notes 1, 2 PG-1500 control program PROM programmer Programmer adapters connected to a PG-1500
Debugging Tools
IE-78000-R IE-78000-R-A IE-78000-R-BK IE-178018-R-EM IE-78000-R-SV3 IE-70000-98-IF-B In-circuit emulator common to 78K/0 Series In-circuit emulator common to 78K/0 Series (for the integration debugger) Break board common to 78K/0 Series Emulation board common to PD178018A Subseries Interface adapter and cable when using EWS as a host machine (for IE-78000-R-A) Interface adapter when using the PC-9800 Series (except notebooks) as a host machine (for IE-78000-R-A) IE-70000-98N-IF Interface adapter and cable when using the PC-9800 Series notebook as a host machine (for IE-78000-R-A) IE-70000-PC-IF-B EP-78230GC-R EV-9200GC-80 EV-9900 SM78K0 ID78K0
Notes 5, 6, 7
Interface adapter when using IBM PC/ATTM as a host machine (for IE-78000-R-A) Emulation probe common to PD78234 Subseries Socket for mounting on target system board created for 80-pin plastic QFP (GC-3B9 type) Jig used when removing the PD178P018AKK-T from the EV-9200GC-80. 78K/0 Series common system simulator Integration debugger for IE-78000-R-A IE-78000-R screen debugger
Notes 4, 5, 6, 7 Notes 1, 2 Notes 1, 2, 4, 5, 6, 7, 8
SD78K/0
DF178018
PD178018A Subseries device file
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PD178004A, 178006A, 178016A, 178018A
Real-Time OS
RX78K/0 Notes 1, 2, 3, 4 MX78K0
Notes 1, 2, 3, 4
78K/0 Series real-time OS 78K/0 Series OS
Notes 1. 2. 3. 4. 5. 6. 7. 8.
PC-9800 Series (MS-DOS TM) based IBM PC/AT and compatible (PC DOSTM /IBM-DOSTM /MS-DOS) based HP9000 Series 300 TM based HP9000 Series 700 TM (HP-UXTM ) based, SPARCstationTM (SunOSTM) based, EWS4800 Series (EWS-UX/V) based PC-9800 Series (MS-DOS + WindowsTM ) based IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based NEWS TM (NEWS-OSTM ) based Under development
Fuzzy Inference Development Support System
FE9000 Note 1/FE9200 Note 2 FT9080 FI78K0
Note 1
Fuzzy knowledge data creation tool Translator Fuzzy inference module Fuzzy inference debugger
/FT9085
Note 3
Notes 1, 3 Notes 1, 3
FD78K0
Notes 1. PC-9800 Series (MS-DOS) based 2. IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS + Windows) based 3. IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS) based Remarks 1. Please refer to the 78K/0 Series Selection Guide (U11126E) for information on third party development tools. 2. The RA78K/0, CC78K/0, SD78K/0, ID78K/0, SM78K/0 and RX78K/0 are used in combination with the DF178018.
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PD178004A, 178006A, 178016A, 178018A
APPENDIX C. RELATED DOCUMENTS
Device Documents
Title Document No. (Japanese) Document No. (English)
PD178018A Subseries User's Manual
78K/0 Series User's Manual--Instruction 78K/0 Series Instruction Set 78K/0 Series Instruction Table
To be prepared
U12326J U10904J U10903J
To be prepared
U12326E -- -- -- U10121E
PD178018A Subseries Special Function Register Table
78K/0 Series Application Note Basics (II)
To be prepared
U10121J
Development Tool Documents (User's Manual)
Title RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor RA78K0 Assembler Package Operation Assembly Language Structured Assembly Language CC78K Series C Compiler Operation Language CC78K/0 C Compiler Operation Language CC78K/0 C Compiler Application Notes CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS) Based PG-1500 Controller IBM PC Series (PC DOS) Based IE-78000-R IE-78000-R-A IE-78000-R-BK IE-178018-R-EM EP-78230 SM78K0 System Simulator Windows Based SM78K Series System Simulator Reference External Parts User open Interface Specifications Reference Reference Guide Introduction Reference SD78K/0 Screen Debugger IBM PC/AT (PC DOS) Based Introduction Reference Programming Know-how EEU-656 EEU-655 U11517J U11518J EEA-618 U12322J U11940J EEU-704 EEU-5008 U11376J U10057J EEU-867 U10668J EEU-985 U10181J U10092J EEU-1280 EEU-1284 U11517E U11518E EEA-1208 -- EEU-1335 EEU-1291 U10540E U11376E U10057E EEU-1427 U10668E EEU-1515 U10181E U10092E Document No. (Japanese) EEU-809 EEU-815 EEU-817 U11802J U11801J U11789J Document No. (English) EEU-1399 EEU-1404 EEU-1402 U11802E U11801E U11789E
ID78K0 Integrated Debugger EWS Based ID78K0 Integrated Debugger PC Based ID78K0 Integrated Debugger Windows Based SD78K/0 Screen Debugger PC-9800 Series (MS-DOS) Based
U11151J U11539J U11649J EEU-852 U10952J EEU-5024 U11279J
U11151E U11539E U11649E U10539E -- EEU-1414 U11279E
Caution The contents of the above documents are subject to change without notice. Please ensure that the latest versions are used in design work, etc. 51
PD178004A, 178006A, 178016A, 178018A
Related Documents for Embedded Software (User's Manual)
Title 78K/0 Series Realtime OS Basics Installation 78K/0 Series OS MX78K0 Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System--Translator 78K/0 Series Fuzzy Inference Development Support System--Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System --Fuzzy Inference Debugger EEU-858 EEU-921 EEU-1441 EEU-1458 Basics Document No. (Japanese) U11537J U11536J U12257J EEU-829 EEU-862 Document No. (English) -- -- -- EEU-1438 EEU-1444
Other Documents
Title IC Package Manual Semiconductor Device Mounting Technology Manual Quality Guides on NEC Semiconductor Devices NEC Semiconductor Device Reliability and Quality Control Electrostatic Discharge (ESD) Test Semiconductor Device Quality Assurance Guide Microcomputer-related Product Guide (Products by other Manufacturers) Document No. (Japanese) C10943X C10535J C11531J C10983J MEM-539 C11893J U11416J C10535E C11531E C10983E -- MEI-1202 -- Document No. (English)
Caution The contents of the above documents are subject to change without notice. Ensure that the latest versions are used in design work, etc.
52
PD178004A, 178006A, 178016A, 178018A
[MEMO]
53
PD178004A, 178006A, 178016A, 178018A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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PD178004A, 178006A, 178016A, 178018A
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290
NEC Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96. 8
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PD178004A, 178006A, 178016A, 178018A
Purchase of NEC I2 C components conveys a license under the Philips I 2C Patent Rights to use these components in an I2 C system, provided that the system conforms to the I2 C Standard Specification as defined by Philips.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. HP9000 Series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or reexport of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5
56

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